1. Field of the Invention
This invention relates generally to the structure and fabrication process of trenched DMOS power transistors. More particularly, this invention relates to a novel and improved structure and process for fabricating high density trenched DMOS power device with strengthened device ruggedness by inducing the avalanche breakdown to occur in the deep body regions near the gate runners, outside of the active area, and in the termination area rather than in the core cell areas underneath the DMOS transistor cells.
2. Description of the Prior Art
Many cell structures are disclosed for the purpose of strengthening the device ruggedness and one example of such devices is disclosed in U.S. Pat. No. 5,072,266 by Bulucea et al. Referring to FIG. 1 for the cell structure of this trench DMOS transistor. The trench DMOS transistor by Bulecea et al. as shown in FIG. 1 provides the advantages that this device has a good ruggedness because of a deep p+ body which is made deeper than the trench gate. Bulucea et al. disclose a device structure and fabrication method to achieve a controlled bulk semiconductor breakdown. The object of prevent a trench surface breakdown by controlling a bulk breakdown is achieved by taking advantage of the position of the gate in the trench and by using a two dimensional "field-shaping" doping profile including a central deep p+ layer that is laterally adjacent to a p body layer and vertically adjacent to an epitaxial layer of appropriate thickness. The device disclosed by this invention provides an improved device profile to suppress the surface breakdown. The transistor also has a good gate oxide integrity at the bottom of the trench gate since the avalanche breakdown is directed to occur below the deep p+ body.
However, even with improved device ruggedness, the device structure disclosed by Bulecea et al. is not suitable for making trench DMOS device with smaller cell size. The reason of this limitation can be explained by referring to FIG. 1 for the patented device profile wherein the p-body regions 25 is formed to be deeper than the trench 40. The deep p-body regions 25 in the trench DMOS 70 disclosed by Bulucea et al. generate an undesirable side effect of creating the JFET regions between the deeper p-body thus causing the JFET resistance R-JFET to increase. Particularly for a high density device when the source regions are reduced to smaller dimension, a profile with the deeper p-body regions extend beneath the bottom of the trench would further reduce the width of the JFET regions thus causing further increase of the JFET resistance. Moreover, the threshold voltage of a device Vth is significantly increased due to a lateral diffusion of the p+ dopant to touch the channel regions.
In order to overcome this limitation, Ueno discloses in a U.S. Pat. No. 5,086,007, entitled "Method of manufacturing an insulated Field Effect Transistor" (issued on Feb. 4, 1992), an improved insulated gate field effect transistor, e.g., a power MOSFET or an insulated gate bipolar transistor (IGBT). The structure of the Ueno's transistor which is formed in a semiconductor substrate with the drain, gate and source regions vertically disposed is shown in FIG. 2 as a cross sectional view. This vertical MOSFET device disclosed by Ueno includes a specially configured trench MOSFET transistor cell which is manufactured by a simplified method employing only a trench mask. In Ueno's process, a trench mask is employed to form the trenches first which are then filled with polysilicon as gate material. An etch process is carried out to completely remove the polysilicon layer from the top surface of the substrate and a top portion in the trenches. The P-body implant and diffusion processes are performed to form the p-body followed by insulating the top portion of the trenches with an insulating material. A novel feature of this invention is to form the narrow source regions along the top edges of the trenches by a diffusion process. Narrow diffusion regions are formed by diffusion without requiring a source mask Source contact are then formed over the top surface of the device.
With Ueno's simplified processes, the body and source regions are formed with self alignment after forming the gates in the trenches, the size of the transistor cells can be more conveniently reduced without being limited by the concerns of failure in satisfying a misalignment tolerance requirement. Ueno's invention further provides a simplified manufacture process such that the production cost can be reduced. A Ueno's device as shown in FIG. 2 however presents several technical difficulties. A poor ohmic contact of the source region to the metal contact is produced as a result of this manufacture process. As the source regions are formed by a diffusion process, the source doping concentration at the interface between the contact metal and the source regions is formed with a Gaussian distribution. The dopant concentration drops rapidly along a distance away from the trench edge. Due to a low doping concentration at the interface between the source region and the metal contact, the ohmic contact formed there has a poor performance characteristic. Poor ohmic contact also occurs between metal and p-body due to the p+ region in the device structure. The ruggedness of the device is adversely affected due to a higher sheet resistance over the p-body since the parasitic NPN transistor becomes more susceptible to be incidentally turned on as the body resistance is increased which causes the voltage drop across the body region to increase. Therefore, even with a structure and processing method of manufacture to improve the transistor cell as described above, Ueno's device does not provide a complete and satisfactory solution to overcome the difficulties faced by the industry in an effort to further miniaturize the power DMOS transistors.
Therefore, a need still exits in the art of power device fabrication, particularly for DMOS design and fabrication, to provide a structure and fabrication process that would resolve these difficulties. More specifically, it is preferably that a transistor with a high cell density can be produced with strengthened ruggedness and reduced body resistance and body contact resistance such that the difficulties as discussed above can be resolved.